RESIS: A New Methodology for Register Optimization in Software Pipelining

Software pipelining is a widespread technique to nd an instruction-level parallel schedule for loops. Reducing execution time often results in an increasing demand of resources to execute the loop operations and to store variables. This paper presents a new technique to reduce the register pressure generated by pipelined schedules. The technique nds a new schedule aiming at reducing the number of required registers without modifying the initiation interval of the schedule and the number of resources required to execute the instructions. A two-steps approach is proposed for such a reduction: minimizing the SPAN of the loop and rescheduling operations within a basic block. Experimental results show that further improvements on the schedules found by the best existing techniques can be obtained at the expense of a negligible computational cost.